期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2018
卷号：6
期号：2
页码：1613
DOI：10.15680/IJIRCCE.2018.0602076
出版社：S&S Publications
摘要：This paper introduces a mixed logic design method for line decoders, by combining pass transistor dualvaluelogic, transmission gate logic and static complementary metal-oxide semiconductor. Two new topologies arepresented for the 2-4 decoder, a 14-transistor topology aiming on minimizing transistor count and power dissipationand a 15-transistor topology aiming on high power-delay performance. In each case both normal and inverting decodersare implemented, yielding a total of four new designs. Furthermore, by using mixed-logic 2-4 decoders combined withstandard CMOS postdecoder, designed four new 4-16 decoders. All proposed decoders have full-swinging capabilityand reduced transistor count compared to their conventional CMOS counterparts. Finally, a variety of comparative EZwave simulations at the 130nm (PYXIS GDK) shows that the proposed circuits present a significant improvement inpower and delay, outperforming CMOS in almost all cases.
