期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2018
卷号：6
期号：2
页码：1632
DOI：10.15680/IJIRCCE.2018.0602088
出版社：S&S Publications
摘要：The main objective is to design a high performance implementation of the Givens Rotation in VLSIHardware. The Givens Rotation algorithm has many applications in computer vision (CV) and artificial intelligencearea. Givens Rotation is the major part in the matrix operations like singular value decomposition or eigen value andeigen vector computation, which has many applications. A few examples include –object recognition, face recognitionand dimensionality reduction, principle component analysis etc. These matrix operations involve lot of Givens Rotationapplied in iterative manner. Though the iterative approach of the matrix operations implemented in software givesdecent performance on the high end processors, it’s still slow to compute on low end desktop computers or embeddeddevices. In this scenario, providing a hardware accelerator that can be used to improve the performance of GivensRotation computation is necessary.In this project VLSI architecture for computing the Givens Rotation will be proposed. Thearchitecture will be coded using Verilog HDL language. The design will be simulated to see the performanceimprovement and synthesized to see the area required by the hardware on FPGA.Tools:Altera quartus II Modelsim simulatorLanguage: Verilog HDL Language.
关键词：Givens Rotation; Singular value decomposition; FPGA; HDL.
