期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2017
卷号：6
期号：10
页码：1624-1634
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Residue Number System (RNS) is the important research area from last five decades. Forward & backward conversion process is the bottle neck which limits the use of RNS for computing needs.. In this paper, we proposed an efficient VLSI architecture for Matrix based RNS backward converter. We analyzed the performance of proposed architecture for different modulo sets of size up to ten. Implemented using TSMC standard cell 180 nm CMOS technology libraries and result analysis indicated that, the performance of proposed converter achieved about 59% area reduction and 30% efficient with respective to Time-Delay Product when compared to the state of art Backward converters.There is performance degradation in computing hardware built based on Weighted Number Systems (WNSs) due to the carry propagation phenomenon inherent to WNSs. The reduction/elimination of carry chains is the major challenge in improving computer arithmetic performance. Several approaches have been proposed like carry look ahead, prefix calculations, anticipated calculation, and alternative number representation systems, Residue Number Systems (RNS). RNS, which is the research topic has interesting inherent characteristics such as parallelism, modularity, fault tolerance, and carry free operations. For this reason it has been utilized in Digital Signal Processing (DSP) applications.
关键词：CMOS; Residue Number System (RNS); Weighted Number Systems (WNSs).
