期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：1
页码：217
DOI：10.15680/IJIRCCE.2017.0501031
出版社：S&S Publications
摘要：A carry skip adder (CSKA) structure has the high speed and very low power consumption. The speed ofthe structure is achieved by concatenation of all the blocks. The incrimination blocks are used to improve the efficiencyof the carry skip adder structure. In existing method multiplexer logic is used, the proposed structure uses the ANDOR-Invert (AOI) and OR-AND-Invert (OAI) for the skip logic. This work uses a simple and efficient gate-levelmodification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-bsquare-root CSLA (SQRT CSLA) architecture. The speed enhancement is achieved by combining concatenation andincrementation schemes to conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexerlogic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for theskip logic. The structure may be realized with both fixed stage size (FSS) and variable stage size (VSS) styles, whereinthe latte r further improves the speed and energy parameters of the adder. Finally
关键词：Carry skip adder (CSKA); energy efficient; high performance; hybrid variable latency Adders; voltage;scaling
