期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：1
页码：781
DOI：10.15680/IJIRCCE.2017.0501166
出版社：S&S Publications
摘要：An proficient implementation in the area of field programmable gate array (FPGA) by using both binaryGolay code (G23) and extended binary Golay (G24) can be performed with the help of number of encoding scheme suchas block code, Turbo codes, Hamming code, CRC-cyclic redundancy check-based etc. High speed with less complexityand low-latency architecture is the main concern area when working on FPGA. To avoid the complexity and for theaccomplishment of the need of the system this paper present a review on number of scholars and on the bases of that anew scheme is proposed in future for FPGA using both binary Golay code (G23) and extended binary Golay (G24).
