期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：2
页码：2317
DOI：10.15680/IJIRCCE.2017.0502043
出版社：S&S Publications
摘要：Adders and multipliers are fundamental building blocks in many computational units. The project isimplemented on Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standardconventional logic gates/cells, based on complementary pass transistor logic and have been validated with simulations,a layout vs. schematic check, and a design rule check. It is proved that the proposed multiplier is better and optimized,compared to its existing counterparts with respect to the number of gates, constant inputs, garbage outputs, hardwarecomplexity, and number of transistors required. The Baugh-Wooley multipliers exhibit comparable delay, less powerdissipation and smaller area.
关键词：Wallace signed multiplier; Baugh-Wooley approach; and standard conventional logic cells.
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