期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：2
页码：2424
DOI：10.15680/IJIRCCE.2017.0502076
出版社：S&S Publications
摘要：This paper proposes the design of VLSI architecture for image compression. To perform the process ofimage compression, VLSI architecture is designed using lifting-based discrete wavelet transform (DWT) and it isimplemented in Spartan 3EDK kit. The lifting-based DWT architecture has the advantage of lower computationalcomplexity and higher efficiency. Through the DWT, signals can be decomposed into different sub bands with bothtime and frequency information. Traditional DWT architectures are based on convolution. The second-generationDWTs, which are based on lifting algorithms, are proposed. Compared with convolution-based, lifting-basedarchitectures are not only having lower computation complexity but also require less memory. Here we proved theimage compression by using Micro-blaze core processor with the help of XILINX platform studio Design suite. Thealgorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with thePC using the RS232 cable. In this proposed system, the core processor Micro-blaze is converted into a lifting basedDWT architecture. The test results are seen to be satisfactory.
