期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：3
页码：4657
DOI：10.15680/IJIRCCE.2017.0503193
出版社：S&S Publications
摘要：Data communication basically involves the transfer of data from one point to another. Error may beoccurred by the channel which makes the data unreliable for user and hence we have different error detection andcorrection schemes. This paper proposes the viterbi algorithm for error detection and correction by using trellismethod. In the data transmission, the error detection and correction with minimum latency and buffering is a majorproblem. This paper uses virtual channel to increase the throughput and efficiency of the system. It is the routerwhich is used to move message and reply on different channels and never have loop on a single channel. Deadlockcan be avoided during transmission. The viterbi algorithm uses feed forward control which means the error can beidentified before processing the data. In this paper, the viterbi algorithm having the capability of correcting up to 8 bitsand it doesn’t need any separate buffer for storing the error bits.Then we implement the design using Verilog, then simulated and synthesized using Modelsim SE 6.5 simulator andXilinx ISE 13.2i respectively.
