期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：3
页码：4930
DOI：10.15680/IJIRCCE.2017.0503235
出版社：S&S Publications
摘要：Modifying any type digital based hardware architecture and reducing the hardware system power, it’sspeed and the complexity level where VLSI technology is used . The process of filtering is mainly used in DSP andDIP real world applications as well and its work is to remove the noise in original signal or image. The filterarchitecture with an optimized process is used for reducing its processing time and to increase the performance of thesystem. In several digital signal processing (DSP) area adaptive digital filters find wide applications.Here a lowcomplexityfilter design using the MCM scheme is presented with block implementation of fixed FIR filterstheproposed structure involves significantly less energy per sample (EPS) and less area delay product (ADP) than theexisting block implementation of direct-form structure for medium or large filter lengths, while for the short-lengthfilters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure.From the simulation results, we find that the proposed design offers large efficient output when compared to theexisting outputs. Here the digital architecture based VLSI technology is used to modify the FIR filter architecture andthis architecture uses a novel partial product generator which is generally used to alter the efficient architecture inorderto implement a delayed least mean square adaptive filter by using three co-efficient input.This algorithm is used toreduce the path delay and also to improve the speed when compare to proposed methodology.
