期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：8
页码：15536
DOI：10.15680/IJIRSET.2016.0508212
出版社：S&S Publications
摘要：With modern technology, power dissipation, delay and area have become major and vital constraints inthe electronic industry. Gate diffusion Input (GDI) is a technique that lowers power dissipation; delay by using lessNo.of transistors i.e. with low area. This paper describes the design of a 32 bit Parallel Self Timed Adder (PASTA)using GDI logic for low area, high speed and low power applications. PASTA is an asynchronous adder which worksusing a recursive formulation for performing multi-bit binary addition. The PASTA worked in a parallel manner for thebits which do not require any carry chain propagation. PASTA design is simple which uses multiplexers and half adder.All the carriers are detected using a completion signal detection unit to terminate the recursive operation. Mentorgraphics 130nm Pyxis schematic editor and Eldo simulator are used for simulation. The simulation results show that theproposed model attains better power consumption, delay and reduction in the number of transistors.
