期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：9
页码：16429
DOI：10.15680/IJIRSET.2016.0509128
出版社：S&S Publications
摘要：The Least Mean Square adaptive filters are widely used in signal processing, measurement and analysisof continuously changing parameters and signal analysis. The conventional LMS algorithm does not support pipelinedimplementation because of its recursive behaviour thus it is modified to a form called the delayed LMS (DLMS)algorithm, which allows pipelined implementation of the filter. Existing architectures for the LMS algorithm withdelayed coefficient adaptation have large adaptation delay and the convergence behaviour gets degraded. The main aimof this project is to reduce the area-delay product, adaptation delay and mean square error of a Delayed Least MeanSquare (DLMS) adaptive filter. For achieving lower adaptation-delay and area-delay efficient implementation, a partialproduct generator is used. For further reducing the delay we are using Parallel Prefix Adders in partial productgenerator. The proposed structures are synthesized using Xilinx ISE Design suite 14.2 and implemented on Spartan6.From the comparison of these structures we can see that the Partial Product Generator (PPG) architecture is the best forimplementation of lower delay adaptive filter.
关键词：Least mean square adaptive filter; parallel prefix adder.
