期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：11
页码：19403
DOI：10.15680/IJIRSET.2016.0511125
出版社：S&S Publications
摘要：Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design,and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient2-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique.Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancyexisting in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value andany level of decomposition. The parallel structure has 100% hardware utilization efficiency.
