期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：12
页码：20403
DOI：10.15680/IJIRSET.2016.0512022
出版社：S&S Publications
摘要：The realization of Multiplication operation is essential for most of the scientific applications as well asin commercial applications like banking, accounting, financial analysis, tax calculation, currency conversion, andinsurance etc. Multiplier is a key building block and almost obligatory component in all such applications. That is whyreconfigurable PLDs are equipped with dedicated embedded multipliers. The prerequisite of the multiplierimplementation is that it should be primarily fast and secondarily efficient in terms of power consumption and chiparea. The multiplication involves two basic operations viz. generation of partial products and their accumulation. Tospeed up the multiplication process, one can reduce the number of partial products to be generated and later,accelerating their accumulation. The design of multiplier depends upon the type, range and precision of data to beprocessed by the multiplier block viz. fixed point and floating point numbers represented in binary and decimal format.Since, in electronic computers, binary data can be stored more efficiently and processed faster than decimal data,binary multiplication is suitable for scientific applications due to its mathematical properties and performanceadvantage. However, the decimal format is preferred for many non-scientific applications because of greater precisionand decimal rounding. Thus, current financial, e-commerce and user-oriented applications make an intensive use ofinteger and fractional numbers represented in decimal radix.This paper presents an overview of the development of reconfigurable decimal multipliers. The multiplicationcan be realized using sequential technique where partial products are generated sequentially and each newly generatedproduct is added to previously accumulated partial product. The second method is a parallel multiplier in which partialproducts are generated in parallel and accumulated using a fast multi-operand adder. The third method is an arraymultiplier, where array of identical cells are used for generating new partial products; accumulating themsimultaneously. In this method, no separate circuits are required for generation and accumulation of partial productswhich reduces execution time but increases hardware complexity. There are several designs of decimal multiplierswhich are implemented and synthesized by researchers with improvement in one or more design parameters viz. speed,power, and area. In this paper, the module functionality and performance issues of several designs of decimalmultipliers are compared.
