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  • 标题:Design of Reversible Central Processing Unit Based on Reversible Logic Gate
  • 本地全文:下载
  • 作者:Shachchidanand Nagagach ; Assistant Prof. Deepak Kumar
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2017
  • 卷号:6
  • 期号:1
  • 页码:319
  • DOI:10.15680/IJIRSET.2017.0601054
  • 出版社:S&S Publications
  • 摘要:Power crisis is a vital problem in today’s world. In recent years, the growing market of electronicsystems suffers from power dissipation and delay removal problem. Bennett et al. proved that the one-to-one mappingbetween the inputs and outputs of reversible circuit drastically reduces the power consumption and delay consumed of acircuit.There are four major design parameters of reversible circuits. First is the gate count which is the number of gateare used in the circuit. Second is the quantum delay. Third is the number of ancilla inputs which are constant inputswhich are used to maintain the reversibility of the device. Fourth is the number of garbage outputs i.e. output signalswhich are not used as inputs to other gates and are only there to maintain reversibility. In this paper the survey ofdesign central processing unit based on reversible gate and parameter.
  • 关键词:Reversible Gates; Central Processing Unit (CPU); Garbage Output; Quantum Cost
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