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  • 标题:High Speed Area Efficient VLSI Architecture for DCT using Proposed CORDIC Algorithm
  • 本地全文:下载
  • 作者:Deepnarayan Sinha ; Prashant Chaturvedi ; Dr. Rita Jain
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2017
  • 卷号:6
  • 期号:1
  • 页码:326
  • DOI:10.15680/IJIRSET.2017.0601055
  • 出版社:S&S Publications
  • 摘要:Low-power layout is one of the most vital challenges to maximize battery life in portable devices and tosave the energy during simulation operation. Image and video compressor is widely used in Discrete Cosine Transform(DCT). Many types of techniques are used in design discrete cosine transform (DCT). Multiplier and adder are twomain components in design to DCT, Loeffer (1989) have developed a new architecture DCT, it consists of 11multiplications and 29 additions. By now a day we required low chip area and fast speed algorithm, but the multiplierconsumed large area compared to adder. We are designed to multiplier less CORDIC (Coordinate Rotation DigitalComputer) algorithm based on DCT. CORDIC is a main component of shift and add for rotation vector and plan whichis usually used for calculation of trigonometric functions. CORDIC algorithm is efficient area and delay compared toexisting algorithms. All design are implementation Xilinx 14.1i and verified the result.
  • 关键词:Discrete Cosine Transform; Discrete Fourier Transform; Coordinate Rotation Digital Computer
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