期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：2
页码：2031
DOI：10.15680/IJIRSET.2017.0602105
出版社：S&S Publications
摘要：The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooleymultiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This systemcontain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a veryefficient leakage control technique called multiple channel conventional multiplier technology. We have designed 16bit Vedic multiplier using Carry-Save technology and used comparative simulation results that indicate theperformance of the circuit. Vedic mathematics is a ancient Indian mathematics is very useful for doing tedious andcumbersome mathematical calculation at a very fast rate. The Vedic multiplier is approximately 10 times fasterperformance than the conventional multiplier architecture. Experiments show that our proposed multiplier schemeshave only shorter delay with respect to a conventional Booth radix-4 multiplier schemes.
