期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：3
页码：4337
DOI：10.15680/IJIRSET.2017.0603103
出版社：S&S Publications
摘要：The micro architecture of digital FIR filter consists of a data path and a control unit. The data path is thecomputational engine of FIR filter and mainly consists of Decoders, adders, multipliers and delay elements. Thehardware implementation of a Serial and parallel digital FIR filter architecture using a micro programmed controller ispresented. The main advantage of the micro programmed controller is its flexibility in modifying the micro programstored in ROM based control memory. To improve the performance of FIR filter, an efficient multiplier is required.Wallace tree and Vedic multipliers are used for the implementation of serial and parallel micro programmed FIR filterarchitectures we have proposed a novel high speed and area efficient Vedic multiplier using compressors is used for theimplementation of serial and parallel micro programmed FIR filter architectures. The proposed technique, a 4-tap serialand parallel FIR filter is implemented using Xilinx Spartan 3E FPGA. The proposed FIR filter is coded in VERILOG.The design can be easily modified to implement higher-order and high speed FIR filters which are commonly used invideo and image processing applications.
