期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：4
页码：5367
DOI：10.15680/IJIRSET.2017.0604036
出版社：S&S Publications
摘要：Nowadays, low power design has significant importance in digital VLSI Circuits. In this paper two newdesigns are proposed for the low power 4 bit modified Vedic Multiplier with less number of Transistors using theUrdhva Tiryagbhyam (UT) sutra .The topology used to reduce the power and the area is Modified GDI-MUX technique.These low power designs are realized in CADENCE VIRTUSO schematic tool.
