期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：4
页码：7119
DOI：10.15680/IJIRSET.2017.0604242
出版社：S&S Publications
摘要：In the digital signal processing (DSP) domain, Hardware acceleration is proved an extremely promisingimplementation strategy. Instead of adopting a monolithic application-specific integrated circuit design approach, anovel accelerator architecture comprising flexible arithmetic components that support the execution of a large set ofoperation templates found in DSP kernels is introduced. One of its major peculiarity is to enable computations to beaggressively performed with carry-save (CS) formatted data. Incorporation of Error Tolerant Adder is anotherspeciality. Advanced arithmetic design concepts, i.e., recoding techniques, and more enhanced arithmetic componentsare utilized enabling CS optimizations to be performed in a larger scope than in previous approaches.
