期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：4
页码：7132
DOI：10.15680/IJIRSET.2017.0604244
出版社：S&S Publications
摘要：In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessityofportable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors toperform fast arithmetic functions. In this project, an area-efficient carry select adder by sharing the common Booleanlogic term (CBL) is used. After logic simplification and sharing partial circuit, only one XOR gate and one invertergate in each summation operation as well as one AND gate and one inverter gate ineach carry-out operation are needed.Through the multiplexer, the correct output is selected according to the logic states of the carry in signal.The modifieddesign has been developed using Binary to Excess-1 converter (BEC). The new design has reduced area and delay ascompared with the regular SQRT CSLA design. The result analysis shows that the newly designed SQRT CSLAstructure is better than the regular SQRT CSLA.
