期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：5
页码：8511
DOI：10.15680/IJIRSET.2017.0605203
出版社：S&S Publications
摘要：As the technology is improved to support very large chip sizes, the system designers have faced withpower consumption and leakage current problems. The CMOS technology has increased in level of importance to thepoint where it now clearly holds center stage as the dominant VLSI technology. The Self controllable Voltage Level(SVL) technique is used in DRAM 4×4 (Dynamic Random Access Memory) to reduce leakage current. By using SVLtechnique the leakage current reduce up to some extent. Further the Variable body biasing technique (VBB) is used toreduce ultra low power consumption and leakage currents. By using Body Biasing technique threshold voltage can becontrolled. With the increase of the threshold voltage leakage current decreases resulting in a decrease in Static Poweror Leakage power. The sleepy transistors are used to achieve ultra low leakage power consumption. When the circuit isin active mode, there is now voltage difference between the body and source in the sleep transistors as the addedtransistors are ON and also offer no resistance between the body and source which means body and source are short.When the circuit is in sleep mode there is a high resistance between body and source resulting in a higher thresholdvoltage (Vth). Consequently, the leakage power consumed reduces. Moreover, due to low Vth during active mode delayremains in a reasonable range. The simulation result shows that the power consumption has been reduced by usingVariable Body Biasing technique compared to SVL technique for implementing DRAM.
关键词：DRAM; self controllable voltage level technique; Variable body bias technique; VLSI.
