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  • 标题:A High-Throughput VLSI Architecture for SC-FDMA MIMO Detectors
  • 本地全文:下载
  • 作者:K.Keerthana ; G.Jyoshna
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2017
  • 卷号:6
  • 期号:6
  • 页码:12291
  • DOI:10.15680/IJIRSET.2017.0606300
  • 出版社:S&S Publications
  • 摘要:Large-scale multiple-input multiple output is termed to be one of the key technology in future generationmultiple cellular systems supporting the 3GPP LTE. LTE includes MIMO technology with orthogonal frequencydivision-multiple access technology surrounded by the downlink and single carrier-frequency division multiple access(SC-FDMA). This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailoredfor single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardwareimplementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimummean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in theconstellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is alsointroduced achieving a superior performance compared to the conventional MMSE detectors. The performance of theproposed design is close to the existing maximum likelihood post-detection processing (ML-PDP) scheme, whileresulting in a significantly lower complexity, i.e., and times fewer Euclidean distance (ED) calculations in the 16-QAMand 64-QAM schemes, respectively.
  • 关键词:ASIC implementation; LTE; MIMO; PDP; SC-FDMA; soft decoding.
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