期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：5
页码：9618
DOI：10.15680/IJIRCCE.2017.0505157
出版社：S&S Publications
摘要：A typical The need of high speed multiplier is increasing as the need of increasing high speedprocessors. A multiplier is one of the hardware blocks in most fast processing system. This is not only a high delayblock but also a major source of power dissipation. A conventional processor requires substantially more hardwareresources and more processing time in the multiplication operation, rather than addition and subtraction. In this project,we implement a high speed Multiplier using algorithm mentioned in Indian ancient Vedic mathematics which isutilized for all case of multiplication and to improve the performance of multiplier. In this method, as the number ofmultiplier bits increases it requires less number of calculations compare to other existing multiplication Algorithm. Inthis paper the Vedic multiplier is compared with the existing method such as booth and array multiplier. The Vedicmultiplier is designed using Urdhva and Nikhilam sutras. This algorithm reduces the overall delay of the multiplierunit.
关键词：Vedic Multiplier; Image Processing; Digital Signal processing; Urdhava Tiryakbhyam sutra
