期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：5
页码：10367
DOI：10.15680/IJIRCCE.2017.0505362
出版社：S&S Publications
摘要：Area, power and delay are the governing parameters in a digital signal processing circuits with FIR –Finite Impulse Response filters being an important element of it. The architecture of FIR filter contains basically 3components- Multiplier, Adder and Delay unit. Multiplication is the reason of area, delay and power consumption indigital circuits and so here also the performance is dependent on multiplier in FIR filter. Research and development isdone to develop multipliers with high speed, less area, low power consumption etc. In this paper we have designed afinite impulse response filter using Wallace multiplier. This multiplier improves the performance parameters- delay,area and power of FIR filters. Xilinx ISE software is used for the synthesis of Wallace multiplier based FIR filter andcode is written in VHDL language and the hardware design implementation is done in Spartan-3 FPGA.
