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  • 标题:Analysis of Low Power D Flip-Flop and Latches for Reduced Power
  • 本地全文:下载
  • 作者:Akash S. Band ; Vishal D. Jaiswal
  • 期刊名称:International Journal of Innovative Research in Computer and Communication Engineering
  • 印刷版ISSN:2320-9798
  • 电子版ISSN:2320-9801
  • 出版年度:2017
  • 卷号:5
  • 期号:6
  • 页码:12392
  • DOI:10.15680/IJIRCCE.2017.0506178
  • 出版社:S&S Publications
  • 摘要:Shift register is sequential logic path to store the digital data, also basic construction block in VLSI path.It is used in many uses, such as digital filters, communication receivers, and image processing ICs. As the size of theimage data residues to rise due to the high request for high quality image data. Due to the latches it causes more powerand delay, shift register is designed by using D-Flip flop that the existing connections are performed through the secondlayer and by the second type of metal and its area and power has been calculated and also the simulation results showsin table.
  • 关键词:D-flip-flop; D latches.
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