期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2015
卷号：6
期号：3
页码：15
DOI：10.5121/vlsic.2015.6302
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register(SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture isdesigned and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sampleand hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SARADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADCusing split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC usingSplit array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
关键词：Successive Approximation ; Analog- to- Digital converter; Digital- to- Analog converter; Split array;Charge redistribution
