期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2015
卷号：6
期号：4
页码：51
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：ASIC Implementation of I2C Master bus controller with design of Firm IP core has been proposed in thispaper. I2C is one the most prominent protocol used in on chip communication among sub-systems. Thegeneric design of I2C master controller has ample of features to incorporate vast varieties of applicationand I2C standards. The generic design is slow, congested and require high power. It’s rare to utilize all thefeatures of generic design fully in a single particular application or system. Hence, a modified ASIC designwith specific less features but with better timing, low power requirement and less area overhead, has beenproposed in this paper. This design is specifically apt for digital systems which have serial bus interfacerequirement for on board communication. Moreover, the Firm IP core of I2C Master Controller has beendesigned for ASIC, which makes the design highly portable on any ASIC chips or SOC designs. The firmIPs is best in terms of flexibility and more predictable than commonly found soft IPs. The entire customASIC implementation of proposed design has been done in Cadence Tool chain with 45nm technology usingstandard cell library. A thorough comparison has been done between generic open sourced RTL design ofI2C Controller obtained from Opencores.org and our proposed design.
关键词：Serial bus interfaces; I2C Protocols; ASIC designing; Firm IP Core; on-chip communications; IP designing.
