期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2015
卷号：6
期号：6
页码：11
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Verification remains the most significant challenge in getting advanced SOC devices in market. Theimportant challenge to be solved in the Semiconductor industry is the growing complexity of SOCs.Industry experts consider that the verification effort is almost 70% to 75% of the overall design effort.Verification language cannot alone increase verification productivity but it must be accompanied by amethodology to facilitate reuse to the maximum extent under different design IP configurations. ThisAdvanced reusable test bench development will decrease the time to market for a chip. It will help in codereuse so that the same code used in sub-block level can be used in block level and top level as well thathelps in saving cost for a tape-out of a chip. This test bench development technique will help us to achievefaster time to market and will help reducing the cost for the chip up to a large extent.
关键词：Advanced verification Methodology; Verification Simulation software; Test Bench.
