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  • 标题:BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design
  • 本地全文:下载
  • 作者:Uday Panwar ; Kavita Khare
  • 期刊名称:International Journal of VLSI Design & Communication Systems
  • 印刷版ISSN:0976-1527
  • 电子版ISSN:0976-1357
  • 出版年度:2014
  • 卷号:5
  • 期号:2
  • 页码:1
  • DOI:10.5121/vlsic.2014.5201
  • 出版社:Academy & Industry Research Collaboration Center (AIRCC)
  • 摘要:A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of acircuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSIcircuit has become a major constrain in a battery operated device for technology node below 90nm, as itdrains the battery even when a circuit is in standby mode. Major concern is the leakage even in run timecondition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inheritedby stacking effect when the series transistors are maximized in OFF state condition. This method isindependent of process technology and does not require any additional power supply. This paper gives anoptimized solution of input pattern determination of some small circuit to find minimum leakage vectorconsidering promising and non-promising node which helps to reduce the time complexity of the algorithm.Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standardlogic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell anddifferent logics respectively.
  • 关键词:Active mode Leakage reduction; Standby mode; Minimum Leakage vector (MLV); Transistor Stacking
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