期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：3
页码：37
DOI：10.5121/vlsic.2014.5304
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This paper presents a design of fast voltage controlled delay element based on modified version of lownoise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delayscontrolled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps overcontrol voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is inagreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element toverify its performance.
