期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：4
页码：13
DOI：10.5121/vlsic.2014.5402
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This Domino logic is often the choice for designing high speed CMOS circuits. Often VLSI designerschoose library based approaches to perform technology mapping of large scale circuits involving staticCMOS logic style. Cells designed using Domino logic style have the flexibility to accommodate wide rangeof functions in them. Hence, there is a scope to adopt a library free synthesis approach for circuitsdesigned using Domino logic. In this work, we present an approach for mapping a domino logic circuitusing an On-the-fly technique. First, we present a node mapping algorithm which maps a given Dominologic netlist using On-the-fly technique. Next, using an Equivalence Table, we re-order the cells along thecritical path for delay, area benefit. Finally, we find an optimum re-ordering set which can obtainmaximum delay savings for a minimum area penalty. We have tested the efficacy of our approach with aset of standard benchmark circuits. Our proposed mapping approach (CRDOM) obtained 21%improvement in area and 17% improvement in delay compared to existing work.
关键词：Domino logic; on the fly mapping; library free synthesis; cell re-ordering; critical path
