期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：5
页码：1
DOI：10.5121/vlsic.2014.5501
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full addercell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because oftheir unique characteristics will save energy consumption and decrease the chip area. In this paper wepresented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometertechnology in Different values of temperature and VDD.
关键词：Low power circuit; Carbon Nanotube Filed Effect Transistors; Nano Transistors; Full Adder
