期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：6
页码：29
DOI：10.5121/vlsic.2014.5604
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.And it is a digital circuit comprised of the basic electronics components, which is used to perform variousfunction of arithmetic and logic and integral operations further the purpose of this work is to propose thedesign of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in thisstudy consist of following main functions like addition also subtraction, increment, decrement, AND, OR,NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in theairthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALUcan be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
