期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：6
页码：35
DOI：10.5121/vlsic.2014.5605
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Providing resistance against side channel attacks especially differential power analysis (DPA) attacks,which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges ofdesigners of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phasedual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. The new flip-flop usesinverters that uses the charge recycling technique where charge stored on high output node duringevaluation phase is used to partially charge the low output node in subsequent pre-charge phases. As aresult less charge comes from the power supply thus lowering the power consumption. Simulation results inCadence Virtuoso 45 nm CMOS process show improvement in power consumption in inverter up to 60%while CRTDPL flip-flop consumes around 50% less power compared to TDPL flip-flop.
关键词：Side Channel attacks; Differential Power Analysis (DPA); Sense Amplifier Based Logic (SABL); Three-;Phase Dual-rail Pre-charge logic (TDPL) Charge recycling TDPL
