期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：6
页码：75
DOI：10.5121/vlsic.2014.5608
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：CMOS technology had attained remarkable to progress and advances thus this progress had been achievedby certain downsizing of the MOSFETs. The dimension of the MOSFETs were scaled upon by factor whichhas historically found to be 0.7 in very large scale integration technology, power and delay analysis havebecome crucial design concern. tn this paper we emphasize the comparative study of delay, average powerand leakage power of CMOS inverter in Ultra Deep Submicron Technology range. This study showsvariation of following as follows by delay to UDSM technology and also for average power and leakagepower by diminishing to certain technology. The simulation results are taken for 45nm in Ultra DeepSubmicron Technology range with the help of Cadence Tool and also analyzing the effect of loadcapacitance, transistor width and supply voltage on average power and delay of CMOS inverter of 45nmtechnology. Therefore the analysis has done with the aim to observe about the certain variation in delayand power with variation in transistor width in UDSM CMOS inverter and also had variation in loadcapacitance and supply voltage had been studied
关键词：UDSM; CMOS Inverter; Average Power; Delay; Leakage Power.
