期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2018
卷号：9
期号：3
页码：51
DOI：10.5121/vlsic.2018.9305
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This report examines the subject of sub threshold leakage on carry save adder. When the gate to sourcevoltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit andthat is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devicesreduces very drastically, and it must be applied in lower power devices since it contributes to low amountof leakage current which confine increases the power consumption of the devices. Adders are the basicbuilding blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficientadders due to its quick and precise computations. Hence this paper performs sub threshold analysis onCSA and the scrutinize results that the total average power is around 4.93μW, the propagation delay forcomplete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
