期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：8
页码：17177
DOI：10.15680/IJIRSET.2017.0608214
出版社：S&S Publications
摘要：LDPC (Low Density Parity Check) is a linear block code that has become one of the most attractiveerror correction codes due to its excellent performance and suitability in high data rate applications. These codes arespecified in terms of parity check matrix (PCM) which is characterized by its sparsity. This PCM can be constructedeither randomly or with structured pattern. This paper presents an overview of different PCM construction algorithms(both random and structured), software implementation of the LDPC decoder using MATLAB, and discusses about theLDPC decoder VLSI implementation using the commercial FPGA, Spartan 3E kit. The main focus is the nominalcomparison between Quasi cyclic LDPC and Random LDPC in terms of area. This quasi cyclic decoder not onlysignificantly reduces the computational complexity due to sparseness, but also the area, in comparison with randomPCM.
关键词：Low Density Parity Check (LDPC); Parity Check Matrix (PCM); Sum Product Algorithm (SPA).
