期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2017
卷号：6
期号：10
页码：19959
DOI：10.15680/IJIRSET.2017.0610140
出版社：S&S Publications
摘要：In this Technical era the high speed and low area of VLSI chip are very- very essential factors. Day byday number of transistors and other active and passive elements are drastically growing on VLSI chip. All theprocessors of the devices adders and multipliers are played an important role. Adder is a striking element for thedesigning of fast multiplier. Ultimately here need a fast adder for high bit addition. In this paper, the implemented oflinear convolution are based on common Boolean logic and baugh multiplier. Proposing common Boolean logic (CBL)adder provides less components, less path delay and better speed compare to other existing CBL adder and otheradders. Here we are comparing the linear convolution of different-different word size from other adders. The designand experiment can be done by the aid of Xilinx 6.2i Spartan device family.
关键词：Common Boolean Logic (CBL); Ripple Carry Adder Linear Convolution; Xilinx
