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  • 标题:Glitch Analysis and Reduction in Combinational Circuits
  • 本地全文:下载
  • 作者:Ronak Shah
  • 期刊名称:Computer Science & Information Technology
  • 电子版ISSN:2231-5403
  • 出版年度:2016
  • 卷号:6
  • 期号:9
  • 页码:33-40
  • DOI:10.5121/csit.2016.60904
  • 出版社:Academy & Industry Research Collaboration Center (AIRCC)
  • 摘要:Hazard in digital circuits is unnecessary transitions due to gate propagation delay in thatcircuit. Hazards occur due to uneven delay offered in the path of the various ongoing signals.One of the important reasons for power dissipation in CMOS circuits is the switching activity.This include activities such as spurious pulses, called glitches. Power optimization techniquesthat concentrate on the reduction of switching power dissipation of a given circuit arecalled glitch reduction techniques. In this paper, we analyse various Glitch reductiontechniques such as Hazard filtering Technique, Balanced Path Technique, Multiple ThresholdTechnique and Gate Freezing Technique. Using simulation, we also measure the parameterssuch as noise and delay of the circuits on application of various techniques to check thereliability of different circuits in various situations.
  • 关键词:Glitch; Power dissipation; Gate freezing; balanced path delay; multiple threshold transistor;Hazard filtering; Noise; Delay and switching activity.
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