出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is anestablished technology and industry standard for on-chip boundary scan testing of SoCs. JTAGTAP controllers are becoming a delivery and control mechanism for Design For Test. Theobjective of this work is to design and implement a TAP controller IP core compatible withIEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the TestMode Persistence controller and its associated logic. This work is expected to serve as a readyto use module that can be directly inserted in to a new digital IC designs with littlemodifications.
