期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2017
卷号：7
期号：6
页码：3323-3331
DOI：10.11591/ijece.v7i6.pp3323-3331
语种：English
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz.
其他摘要：Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz.
关键词：Electronics and Communication Engineering;VLSI Design;Low power VLSI Design;delay locked loop; voltage controlled delay line; differential pair configuration; phase frequency detector; charge pump; loop filter
