期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2014
卷号：4
期号：5
页码：648-657
语种：English
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：In this paper we present the design of a quadrature decoder/counter interface IC (ASIC) that performs the decoding, counting, and bus interface function in digital motor control systems, employing an Altra FLEX 10KA, 2s150fg456 Xilinx device. The ASIC contains a pair of digital filters, a quadrature decoder, an up/down counter, a latch and inhibit circuit, and an 8-bit bus interface to a digital processing system. The design of digital of the digital filter is based on the finite state machine model with datapath (FSMD). A novel scheme for detecting the motor rotation direction is also proposed. The ASIC can be applied to a digital motor control system forgetting the rotation speed or position of the motor, which is quipped with an optical encoder. The data acquisition can be extended to 16-bit integer format by two continuos reading cycles. Simulation and experimental tests are shown to verify the ASIC function properly.DOI:http://dx.doi.org/10.11591/ijece.v4i4.5500
其他摘要：In this paper we present the design of a quadrature decoder/counter interface IC (ASIC) that performs the decoding, counting, and bus interface function in digital motor control systems, employing an Altra FLEX 10KA, 2s150fg456 Xilinx device. The ASIC contains a pair of digital filters, a quadrature decoder, an up/down counter, a latch and inhibit circuit, and an 8-bit bus interface to a digital processing system. The design of digital of the digital filter is based on the finite state machine model with datapath (FSMD). A novel scheme for detecting the motor rotation direction is also proposed. The ASIC can be applied to a digital motor control system forgetting the rotation speed or position of the motor, which is quipped with an optical encoder. The data acquisition can be extended to 16-bit integer format by two continuos reading cycles. Simulation and experimental tests are shown to verify the ASIC function properly. DOI: http://dx.doi.org/10.11591/ijece.v4i4.5500
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