期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2014
卷号：4
期号：3
页码：433-440
语种：English
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and was implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for data rates from 1 kbps to 8 kbps was implemented.DOI:http://dx.doi.org/10.11591/ijece.v4i3.5561
其他摘要：This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and was implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for data rates from 1 kbps to 8 kbps was implemented. DOI: http://dx.doi.org/10.11591/ijece.v4i3.5561
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