期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：6
页码：13-25
DOI：10.5121/vlsic.2013.4602
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：n this paper we present the development of Acceler atable UVCs from standard UVCs in System Verilog and their usage in UVM based Verification Environme nt of Image Signal Processing designs to increase run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for internal control and data buses of ST imaging group by partitioning of transaction-level components an d cycle-accurate signal-level components between the software simulator and hardware accelerator respectively. Standard Co-Emulation API: Modeling I nterface (SCE-MI) compliant, transaction-level communications link between test benches running on a host system and Emulation machine is established . Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing designs both with simulator and emulator as UVM acc eleration is an extension of the standard simulatio n- only UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces developmen t schedule risks while leveraging transaction models used during simulation. In this paper, we discuss our experiences on UVM ba sed methodology adoption on TestBench-Xpress (TBX) based technology step by step. We are also do ing comparison between the run time performance results from earlier simulator-only environment and the new, hardware-accelerated environment. Althoug h this paper focuses on Acceleratable UVC’s developme nt and their usage for image signal processing designs. Same concept can be extended for non-image signal processing designs.
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