期刊名称：International Journal of Advanced Computer Science and Applications(IJACSA)
印刷版ISSN：2158-107X
电子版ISSN：2156-5570
出版年度：2018
卷号：9
期号：12
DOI：10.14569/IJACSA.2018.091201
出版社：Science and Information Society (SAI)
摘要：Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system’s complexity makes the reliability evaluation extremely difficult and costly. Redundancy techniques are widely used to increase the reliability of such systems. These techniques provide a large area & time overheads which cause more power consumption and delay, respectively. An experimental evaluation method is proposed to find critical nodes of the FPGA-based designs, named “hardness analysis technique” under the proposed RASP-FIT tool. After finding the critical nodes, the proposed redundant model is applied to those locations of the design and the code is modified. The modified code is functionally equivalent and is more hardened to the soft-errors. An experimental set-up is developed to verify and validate the criticality of these locations found by using hardness analysis. After applying redundancy to those loca-tions, the reliability is evaluated concerning failure rate reduction. Experimental results on ISCAS’85 combinational benchmarks show that a min-max range of failure reduction (14%-85%) is achieved compared to the circuit without redundancy under the same faulty conditions, which improves reliability.
关键词：Dependability; fault injection; fault tolerance; reli-ability; single event effects
