期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2019
卷号：9
期号：2
页码：950-959
DOI：10.11591/ijece.v9i2.pp950-959
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.
关键词：Congestion;Fault tolerant;Network on chip;Permanent fault;Random arbiter;Routing algorithm;Security;Shortest path routing
其他关键词：fault tolerant;congestion;permanent fault;random arbiter;security;routing algorithm;network on chip;shortest path routing
