期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2019
卷号：9
期号：2
页码：960-966
DOI：10.11591/ijece.v9i2.pp960-966
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：The evolutions in the modern memory units are comeup with FinFET/SRAM which can be utilized over high scaled computing units and in other devices. Some of the recent systems were surveyed through which it is known that existing systems lags with improving the performance and optimization of FinFET/SRAM design. Thus, the paper introduces an optimized model based on Search Optimization mechanism that uses Predictive Approach to optimize the design structure of FinFET/SRAM (PAOD). Using this can achieve significant fault tolerance under dynamic cumpting devices and applications. The model uses mathematical methodology which helps to attain less computational time and significant output even at more simulation iteration. This POAD is cost effective as it provides better convergence of FinFET/SRAM design than recursive design.
