期刊名称：TELKOMNIKA (Telecommunication Computing Electronics and Control)
印刷版ISSN：2302-9293
出版年度：2019
卷号：17
期号：1
页码：362-369
DOI：10.12928/telkomnika.v17i1.10180
出版社：Universitas Ahmad Dahlan
摘要：This paper discusses the design of the architecture of an information fusion processor. This
processor emulates the way of human thinking, namely by drawing conclusions from the obtained
collection of information. Architecture design for this processor is based on Knowledge Growing System
(KGS) algorithm. KGS is a novelty in Artificial Intelligence field. Compared to other AI methods, KGS
focuses on the observation of the process of the knowledge growth within human brain based on
information received from the surrounding environment. By using KGS algorithm, this processor works by
receiving inputs from a set of sensors and possible hypotheses obtained after the processing of the
information. The processor generates a value which is called as Degree of Certainty (DoC), which show
the most possible hypothesis among all alternative ones. The Processor Elements which are used to
perform KGS algorithm is designed based on systolic array architecture. The design of this processor is
realized with VHSIC Hardware Design Language (VHDL) and synthesized by using FPGA Quartus II.13.1.
The results show that the data path which has been design is able to perform the mechanism of KGS
computation.
其他摘要：This paper discusses the design of the architecture of an information fusion processor. This processor emulates the way of human thinking, namely by drawing conclusions from the obtained collection of information. Architecture design for this processor is based on Knowledge Growing System (KGS) algorithm. KGS is a novelty in Artificial Intelligence field. Compared to other AI methods, KGS focuses on the observation of the process of the knowledge growth within human brain based on information received from the surrounding environment. By using KGS algorithm, this processor works by receiving inputs from a set of sensors and possible hypotheses obtained after the processing of the information. The processor generates a value which is called as Degree of Certainty (DoC), which show the most possible hypothesis among all alternative ones. The Processor Elements which are used to perform KGS algorithm is designed based on systolic array architecture. The design of this processor is realized with VHSIC Hardware Design Language (VHDL) and synthesized by using FPGA Quartus II.13.1. The results show that the data path which has been design is able to perform the mechanism of KGS computation.
