期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2018
卷号：9
期号：5
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design andoperating parameters of the SRAM cell. The SRAM design and operating parameters considered in thisinvestigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFETback gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low powertechnology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells withoptimized performance using shorted gate and independent gate low power FinFET models. By optimizingthe design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mVand an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard designparameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginaldecrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters.Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cellswith minimal impact on the subthreshold leakage currents, performance and energy consumption.
