摘要：Relentless efforts in semiconductor technology have driven nanometer-scale miniaturization of transistors, diodes, and interconnections in electronic chips. Free-space writing enables interconnections of stacked modules separated by an arbitrary distance, leading to ultimate integration of electronics. We have developed a free-space method for nanometer-scale wiring on the basis of manipulating a metallic nanotip while applying a bias voltage without radiative heating, lithography, etching, or electrodeposition. The method is capable of fabricating wires with widths as low as 1–6 nm and lengths exceeding 200 nm with a breakdown current density of 8 TA/m2. Structural evolution and conduction during wire formation were analyzed by direct atomistic visualization using in situ high-resolution transmission electron microscopy.
